1. Field of the Invention
The present invention relates to a liquid crystal display device active components.
1. Description of the Prior Art
A known liquid crystal display device is provided such an array of thin film transistors (abbreviated to "TFT" hereinafter) as shown in FIG. 3 which is described in more detail in Japanese Laid-open Patent Publication 60-151615 (1985). The TFT array of the liquid crystal display device comprises a plurality of scanning lines X1 to XM (where M is the total number of the scanning lines), a plurality of signal lines Y1 to YN (where N is the total number of the signal lines), a plurality of TFTs 11, and pixel electrodes 26. The scanning lines X1 to XM are coupled to gate electrodes 21 of their respective TFTs 11 and the signal lines Y1 to YN are coupled to source electrodes 23 of the same. The drain electrode 22 of each TFT 11 is coupled to a pixel electrode 26. A liquid crystal material 13 is sandwiched between the pixel electrode 26 and its opposite electrode 27 constituting a display pixel 14. The display pixel 14 acts as a capacitor in an equivalent circuit and if needed, may be accompanied by a storage capacitor coupled in parallel. The operation of the TFTs 11 will now be described referring to FIG. 3. In operation, such selective pulses P1, P2, P3, . . . as shown in FIG. 4 are applied by a scanning driver circuit to the scanning lines X1, X2, X3, . . . respectively. As shown in FIG. 4, T represents a frame period while M is the number of scanning lines. For example, when only a pulse P1 is fed, the scanning line X1 becomes activated selectively (while the other scanning lines remain unselected) thus allowing each of the TFTs 11 coupled thereto to communicate between its source and the drain and draw a corresponding signal voltage from a signal driver circuit to actuate its pixel. When X1 is unselected, its TFTs become disconnected and hold their signal voltages applied to the pixels until X1 is again selected in the following frame. As understood, the liquid crystal display device with a TFT array is capable of feeding desired signal voltages to corresponding pixels accurately and respectively thus ensuring display of a picture which exhibits less crosstalk and a high contrast ratio.
In production, it is however difficult to have a considerable number of finished TFTs qualified as "good" products, particularly when the number of their scanning and signal lines is increased. Each TFT is constructed in a layer arrangement in which the gate 21, the source 23, and the drain 22 are separated from each other by at least one insulating layer 24, as best shown in the cross sectional view of FIG. 6. Hence, during a procedure of a pinhole forming or other steps, any incidental error tends to cause a shortcircuit between the gate and the source. Accordingly, the shortcircuit between the gate and source electrodes will result in a crucial malfunction of a series of TFTs aligned along the scanning line coupled to the defective TFT which is known as a "line defect". Also, when the source electrode 23 is shortcircuited to the drain electrode 22, their corresponding liquid crystal, cell fails to hold a normal signal voltage thus causing a "point defect".
An improved TFT array has also been introduced in which even if some TFTs are defective, pixel defects (including line defects and point defects) will be minimized, as disclosed in Japanese Laid-open Patent Publication 61-243483 (1986). The improved TFT array is illustrated in FIG. 7 in which each pixel 14 incorporates a plurality of TFTs 11 so that even if one TFT is defective, the remaining TFTs can perform a normal action. However, when such a liquid crystal display device is used for display of alphabetic and numeric characters, the pixel capacitance has to be greater than a parasitic capacitance 28 for the purpose of temperature compensation or other compensation for signal noise and flicker effects. It is apparent that when the capacitance of each pixel 14 in the TFT array is adapted to be greater than the parasitic capacitance 28 of the TFT 11, no trouble arises. In practice, the pixel capacitance across a liquid crystal 13 is insufficient and noise pulses are inducted by a pixel potential via the parasitic capacitance 28 from the scanning line Xi (i=1 to M; M is the total number of the scanning lines) and the signal line Yj (j=1 to N; N is the total number of the signal lines). For a solution, a storage capacitor is arranged in parallel to the display pixel in order to increase the pixel capacitance relative to the parasitic capacitance 28 and thus minimize the noise effect. It is well known that the storage capacitors are formed in an array between corresponding pixel electrodes 26 and a common electrode 29. Although this arrangement is advantageous in the holding of signals, it will be disadvantageous in the cost of fabrication. More particularly, each storage capacitor in the TFT array is arranged by interposing an insulating layer between the pixel electrode 26 and the common electrode 29 and thus, requires an extra number of masking procedures during the production. As the result, a series of the masking procedures will cause the production cost to increase and incidentally, the frequency of production faults will be increased.